A New BIST Architecture for Word Oriented Memory
نویسندگان
چکیده
Systems-on-Chip(SoC)s are now moving from logic dominant to memory dominant chips in order to satisfy high functionality and short development cycle. This means that the yield of memory part is the most important factor for the entire chip yield. In this paper, two word-oriented memory test algorithms are proposed newly. The one is an efficient writing NPSF test algorithm and the other is an efficient disturb test algorithm. Finally, we describe an BIST architecture for word-oriented embedded memory that detects basic FFMs, DFs, NPSFs, and disturb faults.
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تاریخ انتشار 2006